// Copyright © 2023-2025 Advanced Micro Devices, Inc.
// SPDX-License-Identifier: MIT

#include "../shim.bwd_kernel_dq.h"
#include <aotriton/_internal/triton_kernel.h>
#include <aotriton/_internal/kernel_cluster.h>
#include <aotriton/_internal/log.h>
#include <aotriton/cpp_tune.h>
#include <assert.h>
#include <string_view>

#define CURRENT_ENTRY_PUBLIC Autotune_bwd_kernel_dq__A0__F49

#define ARRAY_SIZE(array)  (sizeof(array) / sizeof(array[0]))

namespace { // Anonymous namespace

using namespace std::literals::string_view_literals;

#if AOTRITON_BUILD_FOR_TUNING
// PSels and Copts in JSON String
static const char* kernel_psels[] = {
  R"xyzw({"BLOCK_M": 16, "BLOCK_N": 16, "NUM_XCDS": 8})xyzw",
  R"xyzw({"BLOCK_M": 16, "BLOCK_N": 16, "NUM_XCDS": 8})xyzw",
  R"xyzw({"BLOCK_M": 16, "BLOCK_N": 16, "NUM_XCDS": 8})xyzw",
  R"xyzw({"BLOCK_M": 16, "BLOCK_N": 16, "NUM_XCDS": 8})xyzw",
  R"xyzw({"BLOCK_M": 16, "BLOCK_N": 16, "NUM_XCDS": 8})xyzw",
  R"xyzw({"BLOCK_M": 32, "BLOCK_N": 16, "NUM_XCDS": 8})xyzw",
  R"xyzw({"BLOCK_M": 32, "BLOCK_N": 16, "NUM_XCDS": 8})xyzw",
  R"xyzw({"BLOCK_M": 32, "BLOCK_N": 16, "NUM_XCDS": 8})xyzw",
  R"xyzw({"BLOCK_M": 32, "BLOCK_N": 16, "NUM_XCDS": 8})xyzw",
  R"xyzw({"BLOCK_M": 32, "BLOCK_N": 32, "NUM_XCDS": 8})xyzw",
  R"xyzw({"BLOCK_M": 32, "BLOCK_N": 32, "NUM_XCDS": 8})xyzw",
  R"xyzw({"BLOCK_M": 32, "BLOCK_N": 32, "NUM_XCDS": 8})xyzw",
  R"xyzw({"BLOCK_M": 32, "BLOCK_N": 32, "NUM_XCDS": 8})xyzw",
  R"xyzw({"BLOCK_M": 32, "BLOCK_N": 32, "NUM_XCDS": 8})xyzw",
  R"xyzw({"BLOCK_M": 32, "BLOCK_N": 32, "NUM_XCDS": 8})xyzw",
  R"xyzw({"BLOCK_M": 64, "BLOCK_N": 16, "NUM_XCDS": 8})xyzw",
  R"xyzw({"BLOCK_M": 64, "BLOCK_N": 64, "NUM_XCDS": 8})xyzw",
  R"xyzw({"BLOCK_M": 64, "BLOCK_N": 64, "NUM_XCDS": 8})xyzw",
  R"xyzw({"BLOCK_M": 64, "BLOCK_N": 64, "NUM_XCDS": 8})xyzw",
  R"xyzw({"BLOCK_M": 64, "BLOCK_N": 64, "NUM_XCDS": 8})xyzw"
};
static const char* kernel_copts[] = {
  R"xyzw({"waves_per_eu": 1, "num_warps": 2, "num_stages": 1})xyzw",
  R"xyzw({"waves_per_eu": 2, "num_warps": 2, "num_stages": 1})xyzw",
  R"xyzw({"waves_per_eu": 3, "num_warps": 2, "num_stages": 1})xyzw",
  R"xyzw({"waves_per_eu": 4, "num_warps": 2, "num_stages": 1})xyzw",
  R"xyzw({"waves_per_eu": 4, "num_warps": 4, "num_stages": 1})xyzw",
  R"xyzw({"waves_per_eu": 1, "num_warps": 2, "num_stages": 1})xyzw",
  R"xyzw({"waves_per_eu": 2, "num_warps": 2, "num_stages": 1})xyzw",
  R"xyzw({"waves_per_eu": 3, "num_warps": 2, "num_stages": 1})xyzw",
  R"xyzw({"waves_per_eu": 4, "num_warps": 2, "num_stages": 1})xyzw",
  R"xyzw({"waves_per_eu": 1, "num_warps": 2, "num_stages": 1})xyzw",
  R"xyzw({"waves_per_eu": 1, "num_warps": 4, "num_stages": 1})xyzw",
  R"xyzw({"waves_per_eu": 2, "num_warps": 2, "num_stages": 1})xyzw",
  R"xyzw({"waves_per_eu": 2, "num_warps": 4, "num_stages": 1})xyzw",
  R"xyzw({"waves_per_eu": 3, "num_warps": 2, "num_stages": 1})xyzw",
  R"xyzw({"waves_per_eu": 3, "num_warps": 4, "num_stages": 1})xyzw",
  R"xyzw({"waves_per_eu": 2, "num_warps": 4, "num_stages": 1})xyzw",
  R"xyzw({"waves_per_eu": 1, "num_warps": 2, "num_stages": 1})xyzw",
  R"xyzw({"waves_per_eu": 1, "num_warps": 4, "num_stages": 1})xyzw",
  R"xyzw({"waves_per_eu": 2, "num_warps": 2, "num_stages": 1})xyzw",
  R"xyzw({"waves_per_eu": 2, "num_warps": 4, "num_stages": 1})xyzw"
};
#endif

struct PerfFields {
  int16_t BLOCK_M;
    int16_t BLOCK_N;
    int8_t  NUM_XCDS;
};

static PerfFields image_perf_list [] = {
    { .BLOCK_M = 16, .BLOCK_N = 16, .NUM_XCDS = 8 },
    { .BLOCK_M = 16, .BLOCK_N = 16, .NUM_XCDS = 8 },
    { .BLOCK_M = 16, .BLOCK_N = 16, .NUM_XCDS = 8 },
    { .BLOCK_M = 16, .BLOCK_N = 16, .NUM_XCDS = 8 },
    { .BLOCK_M = 16, .BLOCK_N = 16, .NUM_XCDS = 8 },
    { .BLOCK_M = 32, .BLOCK_N = 16, .NUM_XCDS = 8 },
    { .BLOCK_M = 32, .BLOCK_N = 16, .NUM_XCDS = 8 },
    { .BLOCK_M = 32, .BLOCK_N = 16, .NUM_XCDS = 8 },
    { .BLOCK_M = 32, .BLOCK_N = 16, .NUM_XCDS = 8 },
    { .BLOCK_M = 32, .BLOCK_N = 32, .NUM_XCDS = 8 },
    { .BLOCK_M = 32, .BLOCK_N = 32, .NUM_XCDS = 8 },
    { .BLOCK_M = 32, .BLOCK_N = 32, .NUM_XCDS = 8 },
    { .BLOCK_M = 32, .BLOCK_N = 32, .NUM_XCDS = 8 },
    { .BLOCK_M = 32, .BLOCK_N = 32, .NUM_XCDS = 8 },
    { .BLOCK_M = 32, .BLOCK_N = 32, .NUM_XCDS = 8 },
    { .BLOCK_M = 64, .BLOCK_N = 16, .NUM_XCDS = 8 },
    { .BLOCK_M = 64, .BLOCK_N = 64, .NUM_XCDS = 8 },
    { .BLOCK_M = 64, .BLOCK_N = 64, .NUM_XCDS = 8 },
    { .BLOCK_M = 64, .BLOCK_N = 64, .NUM_XCDS = 8 },
    { .BLOCK_M = 64, .BLOCK_N = 64, .NUM_XCDS = 8 }
};

// u8R generates char8_t which is poorly supported almost everywhere.
// TODO: deduplicate FLATZIP_PATH via shim.cc packed_string
constexpr pstring_view FLATZIP_PATH
#if defined(_WIN32)
{ LR"xyzw(amd-gfx950/flash/bwd_kernel_dq.zip)xyzw" };
#else
{ R"xyzw(amd-gfx950/flash/bwd_kernel_dq.zip)xyzw" };
#endif
constexpr std::string_view FUNC_NAME   { R"xyzw(Q='*fp16:16';BLOCK_DMODEL=64;CAUSAL_TYPE=0;ENABLE_DROPOUT=False;PADDED_HEAD=False;BIAS_TYPE=1)xyzw"   };
constexpr std::string_view ARCH_NAME { R"xyzw(gfx950)xyzw" };

// Checksum can be confirmed with `echo -n '<string>' | b2sum -l 64`
// For example:
//   $ echo -n 'amd-gfx110x/flash/attn_fwd/FONLY__^bf16@16,128,False,False,0,0___gfx1100__P__32_32_0_2_False__CO__wave3_warp2_stg1-Gpu-gfx1100' | b2sum -l 64
//   c4b51ee645d79580  -
static AOTRITON_NS::TritonKernelCompactMeta meta_list[] = {
    { 0xc9f77b80u, 0xfe0c31f4u, 0, 33 }, // c9f77b80fe0c31f4 = b2sum -l 64 <<< amd-gfx950/flash/bwd_kernel_dq.zip;;#F;Q='*fp16:16';BLOCK_DMODEL=64;CAUSAL_TYPE=0;ENABLE_DROPOUT=False;PADDED_HEAD=False;BIAS_TYPE=1;;#P;BLOCK_M=16;BLOCK_N=16;NUM_XCDS=8;;#CO;waves_per_eu=1;num_warps=2;num_stages=1;;arch=gfx950
    { 0xe95b0979u, 0xa6d23fbdu, 0, 73 }, // e95b0979a6d23fbd = b2sum -l 64 <<< amd-gfx950/flash/bwd_kernel_dq.zip;;#F;Q='*fp16:16';BLOCK_DMODEL=64;CAUSAL_TYPE=0;ENABLE_DROPOUT=False;PADDED_HEAD=False;BIAS_TYPE=1;;#P;BLOCK_M=16;BLOCK_N=16;NUM_XCDS=8;;#CO;waves_per_eu=2;num_warps=2;num_stages=1;;arch=gfx950
    { 0x7e9309c2u, 0x3d549a2eu, 0, 113 }, // 7e9309c23d549a2e = b2sum -l 64 <<< amd-gfx950/flash/bwd_kernel_dq.zip;;#F;Q='*fp16:16';BLOCK_DMODEL=64;CAUSAL_TYPE=0;ENABLE_DROPOUT=False;PADDED_HEAD=False;BIAS_TYPE=1;;#P;BLOCK_M=16;BLOCK_N=16;NUM_XCDS=8;;#CO;waves_per_eu=3;num_warps=2;num_stages=1;;arch=gfx950
    { 0x42844aa3u, 0x94f0b1e6u, 0, 153 }, // 42844aa394f0b1e6 = b2sum -l 64 <<< amd-gfx950/flash/bwd_kernel_dq.zip;;#F;Q='*fp16:16';BLOCK_DMODEL=64;CAUSAL_TYPE=0;ENABLE_DROPOUT=False;PADDED_HEAD=False;BIAS_TYPE=1;;#P;BLOCK_M=16;BLOCK_N=16;NUM_XCDS=8;;#CO;waves_per_eu=4;num_warps=2;num_stages=1;;arch=gfx950
    { 0x47a43019u, 0xae8882b1u, 0, 438 }, // 47a43019ae8882b1 = b2sum -l 64 <<< amd-gfx950/flash/bwd_kernel_dq.zip;;#F;Q='*fp16:16';BLOCK_DMODEL=64;CAUSAL_TYPE=0;ENABLE_DROPOUT=False;PADDED_HEAD=False;BIAS_TYPE=1;;#P;BLOCK_M=16;BLOCK_N=16;NUM_XCDS=8;;#CO;waves_per_eu=4;num_warps=4;num_stages=1;;arch=gfx950
    { 0xd11a3639u, 0xf59584d1u, 193, 33 }, // d11a3639f59584d1 = b2sum -l 64 <<< amd-gfx950/flash/bwd_kernel_dq.zip;;#F;Q='*fp16:16';BLOCK_DMODEL=64;CAUSAL_TYPE=0;ENABLE_DROPOUT=False;PADDED_HEAD=False;BIAS_TYPE=1;;#P;BLOCK_M=32;BLOCK_N=16;NUM_XCDS=8;;#CO;waves_per_eu=1;num_warps=2;num_stages=1;;arch=gfx950
    { 0x17b6d42au, 0x4686bb8bu, 193, 73 }, // 17b6d42a4686bb8b = b2sum -l 64 <<< amd-gfx950/flash/bwd_kernel_dq.zip;;#F;Q='*fp16:16';BLOCK_DMODEL=64;CAUSAL_TYPE=0;ENABLE_DROPOUT=False;PADDED_HEAD=False;BIAS_TYPE=1;;#P;BLOCK_M=32;BLOCK_N=16;NUM_XCDS=8;;#CO;waves_per_eu=2;num_warps=2;num_stages=1;;arch=gfx950
    { 0x0c8b3d1eu, 0x6415561du, 193, 113 }, // 0c8b3d1e6415561d = b2sum -l 64 <<< amd-gfx950/flash/bwd_kernel_dq.zip;;#F;Q='*fp16:16';BLOCK_DMODEL=64;CAUSAL_TYPE=0;ENABLE_DROPOUT=False;PADDED_HEAD=False;BIAS_TYPE=1;;#P;BLOCK_M=32;BLOCK_N=16;NUM_XCDS=8;;#CO;waves_per_eu=3;num_warps=2;num_stages=1;;arch=gfx950
    { 0xe409ea46u, 0xc16bf231u, 193, 153 }, // e409ea46c16bf231 = b2sum -l 64 <<< amd-gfx950/flash/bwd_kernel_dq.zip;;#F;Q='*fp16:16';BLOCK_DMODEL=64;CAUSAL_TYPE=0;ENABLE_DROPOUT=False;PADDED_HEAD=False;BIAS_TYPE=1;;#P;BLOCK_M=32;BLOCK_N=16;NUM_XCDS=8;;#CO;waves_per_eu=4;num_warps=2;num_stages=1;;arch=gfx950
    { 0xab81dfc6u, 0xc921b3e9u, 226, 33 }, // ab81dfc6c921b3e9 = b2sum -l 64 <<< amd-gfx950/flash/bwd_kernel_dq.zip;;#F;Q='*fp16:16';BLOCK_DMODEL=64;CAUSAL_TYPE=0;ENABLE_DROPOUT=False;PADDED_HEAD=False;BIAS_TYPE=1;;#P;BLOCK_M=32;BLOCK_N=32;NUM_XCDS=8;;#CO;waves_per_eu=1;num_warps=2;num_stages=1;;arch=gfx950
    { 0xb7dc42e7u, 0x7eda4dafu, 226, 292 }, // b7dc42e77eda4daf = b2sum -l 64 <<< amd-gfx950/flash/bwd_kernel_dq.zip;;#F;Q='*fp16:16';BLOCK_DMODEL=64;CAUSAL_TYPE=0;ENABLE_DROPOUT=False;PADDED_HEAD=False;BIAS_TYPE=1;;#P;BLOCK_M=32;BLOCK_N=32;NUM_XCDS=8;;#CO;waves_per_eu=1;num_warps=4;num_stages=1;;arch=gfx950
    { 0xbc470a70u, 0x3e9b7ed4u, 226, 73 }, // bc470a703e9b7ed4 = b2sum -l 64 <<< amd-gfx950/flash/bwd_kernel_dq.zip;;#F;Q='*fp16:16';BLOCK_DMODEL=64;CAUSAL_TYPE=0;ENABLE_DROPOUT=False;PADDED_HEAD=False;BIAS_TYPE=1;;#P;BLOCK_M=32;BLOCK_N=32;NUM_XCDS=8;;#CO;waves_per_eu=2;num_warps=2;num_stages=1;;arch=gfx950
    { 0xce339790u, 0x8d6dbd60u, 226, 398 }, // ce3397908d6dbd60 = b2sum -l 64 <<< amd-gfx950/flash/bwd_kernel_dq.zip;;#F;Q='*fp16:16';BLOCK_DMODEL=64;CAUSAL_TYPE=0;ENABLE_DROPOUT=False;PADDED_HEAD=False;BIAS_TYPE=1;;#P;BLOCK_M=32;BLOCK_N=32;NUM_XCDS=8;;#CO;waves_per_eu=2;num_warps=4;num_stages=1;;arch=gfx950
    { 0xbf96cb0eu, 0xffe90057u, 226, 113 }, // bf96cb0effe90057 = b2sum -l 64 <<< amd-gfx950/flash/bwd_kernel_dq.zip;;#F;Q='*fp16:16';BLOCK_DMODEL=64;CAUSAL_TYPE=0;ENABLE_DROPOUT=False;PADDED_HEAD=False;BIAS_TYPE=1;;#P;BLOCK_M=32;BLOCK_N=32;NUM_XCDS=8;;#CO;waves_per_eu=3;num_warps=2;num_stages=1;;arch=gfx950
    { 0xe476a87cu, 0x7e4cb2cfu, 226, 478 }, // e476a87c7e4cb2cf = b2sum -l 64 <<< amd-gfx950/flash/bwd_kernel_dq.zip;;#F;Q='*fp16:16';BLOCK_DMODEL=64;CAUSAL_TYPE=0;ENABLE_DROPOUT=False;PADDED_HEAD=False;BIAS_TYPE=1;;#P;BLOCK_M=32;BLOCK_N=32;NUM_XCDS=8;;#CO;waves_per_eu=3;num_warps=4;num_stages=1;;arch=gfx950
    { 0xcede43adu, 0x49f10c41u, 259, 398 }, // cede43ad49f10c41 = b2sum -l 64 <<< amd-gfx950/flash/bwd_kernel_dq.zip;;#F;Q='*fp16:16';BLOCK_DMODEL=64;CAUSAL_TYPE=0;ENABLE_DROPOUT=False;PADDED_HEAD=False;BIAS_TYPE=1;;#P;BLOCK_M=64;BLOCK_N=16;NUM_XCDS=8;;#CO;waves_per_eu=2;num_warps=4;num_stages=1;;arch=gfx950
    { 0x6dbf0eb9u, 0xab4f0ad4u, 365, 33 }, // 6dbf0eb9ab4f0ad4 = b2sum -l 64 <<< amd-gfx950/flash/bwd_kernel_dq.zip;;#F;Q='*fp16:16';BLOCK_DMODEL=64;CAUSAL_TYPE=0;ENABLE_DROPOUT=False;PADDED_HEAD=False;BIAS_TYPE=1;;#P;BLOCK_M=64;BLOCK_N=64;NUM_XCDS=8;;#CO;waves_per_eu=1;num_warps=2;num_stages=1;;arch=gfx950
    { 0x065fa3bfu, 0x946abf7fu, 365, 292 }, // 065fa3bf946abf7f = b2sum -l 64 <<< amd-gfx950/flash/bwd_kernel_dq.zip;;#F;Q='*fp16:16';BLOCK_DMODEL=64;CAUSAL_TYPE=0;ENABLE_DROPOUT=False;PADDED_HEAD=False;BIAS_TYPE=1;;#P;BLOCK_M=64;BLOCK_N=64;NUM_XCDS=8;;#CO;waves_per_eu=1;num_warps=4;num_stages=1;;arch=gfx950
    { 0x3beae664u, 0xf028d727u, 365, 73 }, // 3beae664f028d727 = b2sum -l 64 <<< amd-gfx950/flash/bwd_kernel_dq.zip;;#F;Q='*fp16:16';BLOCK_DMODEL=64;CAUSAL_TYPE=0;ENABLE_DROPOUT=False;PADDED_HEAD=False;BIAS_TYPE=1;;#P;BLOCK_M=64;BLOCK_N=64;NUM_XCDS=8;;#CO;waves_per_eu=2;num_warps=2;num_stages=1;;arch=gfx950
    { 0x10332b75u, 0x15626028u, 365, 398 }, // 10332b7515626028 = b2sum -l 64 <<< amd-gfx950/flash/bwd_kernel_dq.zip;;#F;Q='*fp16:16';BLOCK_DMODEL=64;CAUSAL_TYPE=0;ENABLE_DROPOUT=False;PADDED_HEAD=False;BIAS_TYPE=1;;#P;BLOCK_M=64;BLOCK_N=64;NUM_XCDS=8;;#CO;waves_per_eu=2;num_warps=4;num_stages=1;;arch=gfx950
};

static constexpr int kTotalNumKernels = ARRAY_SIZE(meta_list);

using AOTRITON_NS::v3::flash::autotune::bwd_kernel_dq_packed_string;

static AOTRITON_NS::TritonKernelCluster<kTotalNumKernels>
kernel_cluster(meta_list,
               bwd_kernel_dq_packed_string);

static int8_t lut[1][10][10] =
{
// GPU gfx950_mod0
{{ 7, 9,17,17,19,17,17,19,19,19},
 {15, 2,17,19,17,17,13,13,13,13},
 { 0, 0, 0, 0,13,11,10,13,13,18},
 { 0, 0, 0,11,13,13,12,10,12,16},
 { 1, 2, 2, 9,11,13,12,14,10,10},
 { 2, 0, 3,13,13,12,13,12,14,14},
 { 3, 2, 0,12,13,13,13,12,16,16},
 { 0, 5, 2,13,14,13,13,16,13,14},
 { 1, 3, 1,13,11,16,16,16,16, 4},
 { 3, 7, 7, 6, 6,11,18, 8,13,11}}
// End of GPU gfx950_mod0
}
;

}; // End of anonymous namespace

namespace AOTRITON_NS::v3::flash::autotune {

// using AOTRITON_NS::v2::flash::BwdKernelDqContext;

// Returns the selected kernel_index, or -1 when no valid kernel was selected.
// The kernel_index is logged by the caller (lookup_optimal in shim.cc) so the
// AOTRITON_LOG machinery is not duplicated across every generated autotune TU.
int CURRENT_ENTRY_PUBLIC(BwdKernelDqContext& context, int mod_number) {
#if AOTRITON_BUILD_FOR_TUNING
    constexpr int kLutInTuningModeAlwaysReturnZero = 0;
    AOTRITON_LOG(LOG_DEBUG,
                 "Autotune_bwd_kernel_dq__A0__F49 "
                 "kTotalNumKernels = %d _has_preferred_kernel = %d",
                 kTotalNumKernels, context._has_preferred_kernel);
#ifndef NDEBUG
    assert(bwd_kernel_dq__lut_lambda__0(*context.params, mod_number, lut) == kLutInTuningModeAlwaysReturnZero);
#endif
    int preferred = context._has_preferred_kernel;
    int kernel_index = preferred < 0 ? kLutInTuningModeAlwaysReturnZero : preferred;
#else
    auto kernel_index = bwd_kernel_dq__lut_lambda__0(*context.params, mod_number, lut);
#endif
    if (kernel_index < 0 || kernel_index >= kTotalNumKernels) {
        return -1;
    }
    context.kernel_on_device = kernel_cluster.get(kernel_index);
    context.pp_args_index = 1;
    context.flatzip_path = FLATZIP_PATH;
    // aks2_entry IS the func_name (supplied by f.unified_signature)
    context.aks2_entry   = FUNC_NAME;
    context.func_name = FUNC_NAME;
    context.arch_name = ARCH_NAME;
#if AOTRITON_BUILD_FOR_TUNING
    context._total_number_of_kernels = kTotalNumKernels;
    context._preferred_kernel_psels = kernel_psels[kernel_index];
    context._preferred_kernel_copts = kernel_copts[kernel_index];
#endif
    const auto& perf = image_perf_list[kernel_index];
    context.BLOCK_M = perf.BLOCK_M;
    context.BLOCK_N = perf.BLOCK_N;
    context.NUM_XCDS = perf.NUM_XCDS;
    return kernel_index;
}

#undef CURRENT_ENTRY_PUBLIC
}

// Human-readable Signature 
// Q = "*fp16:16"
// sm_scale = "fp32"
// L = "*fp32:16"
// D = "*fp32:16"
// num_head_q = "i32"
// cu_seqlens_q = "*i32:16"
// num_seqlens = "i32"
// dropout_p = 0
// philox_seed_ptr = 0
// philox_offset2 = 0
// Window_left = 0
// Window_right = 0
// BLOCK_DMODEL = 64
// CAUSAL_TYPE = 0
// ENABLE_DROPOUT = False
// PADDED_HEAD = False
// BIAS_TYPE = 1

// ('SELECT * FROM FLASH$bwd_kernel_dq WHERE gpu IN (?) AND inputs$Q_dtype = ? AND inputs$BLOCK_DMODEL = ? AND inputs$CAUSAL_TYPE = ? AND inputs$ENABLE_DROPOUT = ? AND inputs$PADDED_HEAD = ? AND inputs$BIAS_TYPE = ?', ['gfx950_mod0', 'torch.float16', 64, 0, False, False, 1])

// vim: set fileencoding=utf-8

