// Copyright © 2023-2025 Advanced Micro Devices, Inc.
// SPDX-License-Identifier: MIT

#include "../shim.bwd_kernel_fuse.h"
#include <aotriton/_internal/triton_kernel.h>
#include <aotriton/_internal/kernel_cluster.h>
#include <aotriton/_internal/log.h>
#include <aotriton/cpp_tune.h>
#include <assert.h>
#include <string_view>

#define CURRENT_ENTRY_PUBLIC Autotune_bwd_kernel_fuse__A9__F28

#define ARRAY_SIZE(array)  (sizeof(array) / sizeof(array[0]))

namespace { // Anonymous namespace

using namespace std::literals::string_view_literals;

#if AOTRITON_BUILD_FOR_TUNING
// PSels and Copts in JSON String
static const char* kernel_psels[] = {
  R"xyzw({"BLOCK_M": 16, "BLOCK_N": 16})xyzw",
  R"xyzw({"BLOCK_M": 16, "BLOCK_N": 16})xyzw",
  R"xyzw({"BLOCK_M": 16, "BLOCK_N": 16})xyzw",
  R"xyzw({"BLOCK_M": 16, "BLOCK_N": 16})xyzw",
  R"xyzw({"BLOCK_M": 32, "BLOCK_N": 16})xyzw",
  R"xyzw({"BLOCK_M": 32, "BLOCK_N": 16})xyzw",
  R"xyzw({"BLOCK_M": 32, "BLOCK_N": 32})xyzw",
  R"xyzw({"BLOCK_M": 32, "BLOCK_N": 32})xyzw",
  R"xyzw({"BLOCK_M": 32, "BLOCK_N": 32})xyzw",
  R"xyzw({"BLOCK_M": 64, "BLOCK_N": 16})xyzw",
  R"xyzw({"BLOCK_M": 64, "BLOCK_N": 16})xyzw",
  R"xyzw({"BLOCK_M": 64, "BLOCK_N": 16})xyzw",
  R"xyzw({"BLOCK_M": 64, "BLOCK_N": 16})xyzw",
  R"xyzw({"BLOCK_M": 64, "BLOCK_N": 16})xyzw",
  R"xyzw({"BLOCK_M": 64, "BLOCK_N": 16})xyzw",
  R"xyzw({"BLOCK_M": 64, "BLOCK_N": 32})xyzw",
  R"xyzw({"BLOCK_M": 64, "BLOCK_N": 32})xyzw",
  R"xyzw({"BLOCK_M": 64, "BLOCK_N": 32})xyzw",
  R"xyzw({"BLOCK_M": 64, "BLOCK_N": 32})xyzw",
  R"xyzw({"BLOCK_M": 64, "BLOCK_N": 64})xyzw",
  R"xyzw({"BLOCK_M": 64, "BLOCK_N": 64})xyzw",
  R"xyzw({"BLOCK_M": 64, "BLOCK_N": 64})xyzw",
  R"xyzw({"BLOCK_M": 64, "BLOCK_N": 64})xyzw",
  R"xyzw({"BLOCK_M": 64, "BLOCK_N": 64})xyzw"
};
static const char* kernel_copts[] = {
  R"xyzw({"waves_per_eu": 1, "num_warps": 4, "num_stages": 1})xyzw",
  R"xyzw({"waves_per_eu": 2, "num_warps": 4, "num_stages": 1})xyzw",
  R"xyzw({"waves_per_eu": 3, "num_warps": 4, "num_stages": 1})xyzw",
  R"xyzw({"waves_per_eu": 4, "num_warps": 4, "num_stages": 1})xyzw",
  R"xyzw({"waves_per_eu": 3, "num_warps": 4, "num_stages": 1})xyzw",
  R"xyzw({"waves_per_eu": 4, "num_warps": 4, "num_stages": 1})xyzw",
  R"xyzw({"waves_per_eu": 1, "num_warps": 4, "num_stages": 1})xyzw",
  R"xyzw({"waves_per_eu": 2, "num_warps": 4, "num_stages": 1})xyzw",
  R"xyzw({"waves_per_eu": 4, "num_warps": 4, "num_stages": 1})xyzw",
  R"xyzw({"waves_per_eu": 1, "num_warps": 4, "num_stages": 1})xyzw",
  R"xyzw({"waves_per_eu": 1, "num_warps": 8, "num_stages": 1})xyzw",
  R"xyzw({"waves_per_eu": 2, "num_warps": 4, "num_stages": 1})xyzw",
  R"xyzw({"waves_per_eu": 3, "num_warps": 4, "num_stages": 1})xyzw",
  R"xyzw({"waves_per_eu": 3, "num_warps": 8, "num_stages": 1})xyzw",
  R"xyzw({"waves_per_eu": 4, "num_warps": 4, "num_stages": 1})xyzw",
  R"xyzw({"waves_per_eu": 1, "num_warps": 4, "num_stages": 1})xyzw",
  R"xyzw({"waves_per_eu": 2, "num_warps": 4, "num_stages": 1})xyzw",
  R"xyzw({"waves_per_eu": 3, "num_warps": 4, "num_stages": 1})xyzw",
  R"xyzw({"waves_per_eu": 4, "num_warps": 4, "num_stages": 1})xyzw",
  R"xyzw({"waves_per_eu": 1, "num_warps": 4, "num_stages": 1})xyzw",
  R"xyzw({"waves_per_eu": 2, "num_warps": 4, "num_stages": 1})xyzw",
  R"xyzw({"waves_per_eu": 3, "num_warps": 4, "num_stages": 1})xyzw",
  R"xyzw({"waves_per_eu": 3, "num_warps": 8, "num_stages": 1})xyzw",
  R"xyzw({"waves_per_eu": 4, "num_warps": 4, "num_stages": 1})xyzw"
};
#endif

struct PerfFields {
  int16_t BLOCK_M;
    int16_t BLOCK_N;
};

static PerfFields image_perf_list [] = {
    { .BLOCK_M = 16, .BLOCK_N = 16 },
    { .BLOCK_M = 16, .BLOCK_N = 16 },
    { .BLOCK_M = 16, .BLOCK_N = 16 },
    { .BLOCK_M = 16, .BLOCK_N = 16 },
    { .BLOCK_M = 32, .BLOCK_N = 16 },
    { .BLOCK_M = 32, .BLOCK_N = 16 },
    { .BLOCK_M = 32, .BLOCK_N = 32 },
    { .BLOCK_M = 32, .BLOCK_N = 32 },
    { .BLOCK_M = 32, .BLOCK_N = 32 },
    { .BLOCK_M = 64, .BLOCK_N = 16 },
    { .BLOCK_M = 64, .BLOCK_N = 16 },
    { .BLOCK_M = 64, .BLOCK_N = 16 },
    { .BLOCK_M = 64, .BLOCK_N = 16 },
    { .BLOCK_M = 64, .BLOCK_N = 16 },
    { .BLOCK_M = 64, .BLOCK_N = 16 },
    { .BLOCK_M = 64, .BLOCK_N = 32 },
    { .BLOCK_M = 64, .BLOCK_N = 32 },
    { .BLOCK_M = 64, .BLOCK_N = 32 },
    { .BLOCK_M = 64, .BLOCK_N = 32 },
    { .BLOCK_M = 64, .BLOCK_N = 64 },
    { .BLOCK_M = 64, .BLOCK_N = 64 },
    { .BLOCK_M = 64, .BLOCK_N = 64 },
    { .BLOCK_M = 64, .BLOCK_N = 64 },
    { .BLOCK_M = 64, .BLOCK_N = 64 }
};

// u8R generates char8_t which is poorly supported almost everywhere.
// TODO: deduplicate FLATZIP_PATH via shim.cc packed_string
constexpr pstring_view FLATZIP_PATH
#if defined(_WIN32)
{ LR"xyzw(amd-gfx120x/flash/bwd_kernel_fuse.zip)xyzw" };
#else
{ R"xyzw(amd-gfx120x/flash/bwd_kernel_fuse.zip)xyzw" };
#endif
constexpr std::string_view FUNC_NAME   { R"xyzw(Q='*fp16:16';BLOCK_DMODEL=32;CAUSAL_TYPE=3;ENABLE_DROPOUT=True;PADDED_HEAD=False;BIAS_TYPE=0)xyzw"   };
constexpr std::string_view ARCH_NAME { R"xyzw(gfx1201)xyzw" };

// Checksum can be confirmed with `echo -n '<string>' | b2sum -l 64`
// For example:
//   $ echo -n 'amd-gfx110x/flash/attn_fwd/FONLY__^bf16@16,128,False,False,0,0___gfx1100__P__32_32_0_2_False__CO__wave3_warp2_stg1-Gpu-gfx1100' | b2sum -l 64
//   c4b51ee645d79580  -
static AOTRITON_NS::TritonKernelCompactMeta meta_list[] = {
    { 0x23c9842fu, 0xa0e1f7deu, 328, 350 }, // 23c9842fa0e1f7de = b2sum -l 64 <<< amd-gfx120x/flash/bwd_kernel_fuse.zip;;#F;Q='*fp16:16';BLOCK_DMODEL=32;CAUSAL_TYPE=3;ENABLE_DROPOUT=True;PADDED_HEAD=False;BIAS_TYPE=0;;#P;BLOCK_M=16;BLOCK_N=16;;#CO;waves_per_eu=1;num_warps=4;num_stages=1;;arch=gfx1201
    { 0x4a6ceb28u, 0x8a60f58du, 328, 164 }, // 4a6ceb288a60f58d = b2sum -l 64 <<< amd-gfx120x/flash/bwd_kernel_fuse.zip;;#F;Q='*fp16:16';BLOCK_DMODEL=32;CAUSAL_TYPE=3;ENABLE_DROPOUT=True;PADDED_HEAD=False;BIAS_TYPE=0;;#P;BLOCK_M=16;BLOCK_N=16;;#CO;waves_per_eu=2;num_warps=4;num_stages=1;;arch=gfx1201
    { 0x22086812u, 0x7613810au, 328, 244 }, // 220868127613810a = b2sum -l 64 <<< amd-gfx120x/flash/bwd_kernel_fuse.zip;;#F;Q='*fp16:16';BLOCK_DMODEL=32;CAUSAL_TYPE=3;ENABLE_DROPOUT=True;PADDED_HEAD=False;BIAS_TYPE=0;;#P;BLOCK_M=16;BLOCK_N=16;;#CO;waves_per_eu=3;num_warps=4;num_stages=1;;arch=gfx1201
    { 0xf2b86188u, 0xa650db02u, 328, 390 }, // f2b86188a650db02 = b2sum -l 64 <<< amd-gfx120x/flash/bwd_kernel_fuse.zip;;#F;Q='*fp16:16';BLOCK_DMODEL=32;CAUSAL_TYPE=3;ENABLE_DROPOUT=True;PADDED_HEAD=False;BIAS_TYPE=0;;#P;BLOCK_M=16;BLOCK_N=16;;#CO;waves_per_eu=4;num_warps=4;num_stages=1;;arch=gfx1201
    { 0x0350ded5u, 0xeb0a3f62u, 0, 244 }, // 0350ded5eb0a3f62 = b2sum -l 64 <<< amd-gfx120x/flash/bwd_kernel_fuse.zip;;#F;Q='*fp16:16';BLOCK_DMODEL=32;CAUSAL_TYPE=3;ENABLE_DROPOUT=True;PADDED_HEAD=False;BIAS_TYPE=0;;#P;BLOCK_M=32;BLOCK_N=16;;#CO;waves_per_eu=3;num_warps=4;num_stages=1;;arch=gfx1201
    { 0x2ca13a74u, 0xf9ea61dfu, 0, 390 }, // 2ca13a74f9ea61df = b2sum -l 64 <<< amd-gfx120x/flash/bwd_kernel_fuse.zip;;#F;Q='*fp16:16';BLOCK_DMODEL=32;CAUSAL_TYPE=3;ENABLE_DROPOUT=True;PADDED_HEAD=False;BIAS_TYPE=0;;#P;BLOCK_M=32;BLOCK_N=16;;#CO;waves_per_eu=4;num_warps=4;num_stages=1;;arch=gfx1201
    { 0xe8280be7u, 0x6071dd35u, 430, 350 }, // e8280be76071dd35 = b2sum -l 64 <<< amd-gfx120x/flash/bwd_kernel_fuse.zip;;#F;Q='*fp16:16';BLOCK_DMODEL=32;CAUSAL_TYPE=3;ENABLE_DROPOUT=True;PADDED_HEAD=False;BIAS_TYPE=0;;#P;BLOCK_M=32;BLOCK_N=32;;#CO;waves_per_eu=1;num_warps=4;num_stages=1;;arch=gfx1201
    { 0x3a59ade2u, 0xbd070471u, 430, 164 }, // 3a59ade2bd070471 = b2sum -l 64 <<< amd-gfx120x/flash/bwd_kernel_fuse.zip;;#F;Q='*fp16:16';BLOCK_DMODEL=32;CAUSAL_TYPE=3;ENABLE_DROPOUT=True;PADDED_HEAD=False;BIAS_TYPE=0;;#P;BLOCK_M=32;BLOCK_N=32;;#CO;waves_per_eu=2;num_warps=4;num_stages=1;;arch=gfx1201
    { 0x74a49ac7u, 0x11645a84u, 430, 390 }, // 74a49ac711645a84 = b2sum -l 64 <<< amd-gfx120x/flash/bwd_kernel_fuse.zip;;#F;Q='*fp16:16';BLOCK_DMODEL=32;CAUSAL_TYPE=3;ENABLE_DROPOUT=True;PADDED_HEAD=False;BIAS_TYPE=0;;#P;BLOCK_M=32;BLOCK_N=32;;#CO;waves_per_eu=4;num_warps=4;num_stages=1;;arch=gfx1201
    { 0x851909bdu, 0x58abace0u, 102, 350 }, // 851909bd58abace0 = b2sum -l 64 <<< amd-gfx120x/flash/bwd_kernel_fuse.zip;;#F;Q='*fp16:16';BLOCK_DMODEL=32;CAUSAL_TYPE=3;ENABLE_DROPOUT=True;PADDED_HEAD=False;BIAS_TYPE=0;;#P;BLOCK_M=64;BLOCK_N=16;;#CO;waves_per_eu=1;num_warps=4;num_stages=1;;arch=gfx1201
    { 0x3b88ffedu, 0x71dc9895u, 102, 572 }, // 3b88ffed71dc9895 = b2sum -l 64 <<< amd-gfx120x/flash/bwd_kernel_fuse.zip;;#F;Q='*fp16:16';BLOCK_DMODEL=32;CAUSAL_TYPE=3;ENABLE_DROPOUT=True;PADDED_HEAD=False;BIAS_TYPE=0;;#P;BLOCK_M=64;BLOCK_N=16;;#CO;waves_per_eu=1;num_warps=8;num_stages=1;;arch=gfx1201
    { 0xedfc8487u, 0xf805e8b9u, 102, 164 }, // edfc8487f805e8b9 = b2sum -l 64 <<< amd-gfx120x/flash/bwd_kernel_fuse.zip;;#F;Q='*fp16:16';BLOCK_DMODEL=32;CAUSAL_TYPE=3;ENABLE_DROPOUT=True;PADDED_HEAD=False;BIAS_TYPE=0;;#P;BLOCK_M=64;BLOCK_N=16;;#CO;waves_per_eu=2;num_warps=4;num_stages=1;;arch=gfx1201
    { 0x77410a34u, 0x34fe0efdu, 102, 244 }, // 77410a3434fe0efd = b2sum -l 64 <<< amd-gfx120x/flash/bwd_kernel_fuse.zip;;#F;Q='*fp16:16';BLOCK_DMODEL=32;CAUSAL_TYPE=3;ENABLE_DROPOUT=True;PADDED_HEAD=False;BIAS_TYPE=0;;#P;BLOCK_M=64;BLOCK_N=16;;#CO;waves_per_eu=3;num_warps=4;num_stages=1;;arch=gfx1201
    { 0x28998849u, 0x4f8f248du, 102, 452 }, // 289988494f8f248d = b2sum -l 64 <<< amd-gfx120x/flash/bwd_kernel_fuse.zip;;#F;Q='*fp16:16';BLOCK_DMODEL=32;CAUSAL_TYPE=3;ENABLE_DROPOUT=True;PADDED_HEAD=False;BIAS_TYPE=0;;#P;BLOCK_M=64;BLOCK_N=16;;#CO;waves_per_eu=3;num_warps=8;num_stages=1;;arch=gfx1201
    { 0xc8f942bdu, 0x199ddd9au, 102, 390 }, // c8f942bd199ddd9a = b2sum -l 64 <<< amd-gfx120x/flash/bwd_kernel_fuse.zip;;#F;Q='*fp16:16';BLOCK_DMODEL=32;CAUSAL_TYPE=3;ENABLE_DROPOUT=True;PADDED_HEAD=False;BIAS_TYPE=0;;#P;BLOCK_M=64;BLOCK_N=16;;#CO;waves_per_eu=4;num_warps=4;num_stages=1;;arch=gfx1201
    { 0x4359e3bbu, 0x61cb121cu, 284, 350 }, // 4359e3bb61cb121c = b2sum -l 64 <<< amd-gfx120x/flash/bwd_kernel_fuse.zip;;#F;Q='*fp16:16';BLOCK_DMODEL=32;CAUSAL_TYPE=3;ENABLE_DROPOUT=True;PADDED_HEAD=False;BIAS_TYPE=0;;#P;BLOCK_M=64;BLOCK_N=32;;#CO;waves_per_eu=1;num_warps=4;num_stages=1;;arch=gfx1201
    { 0xab7007abu, 0x3e547bafu, 284, 164 }, // ab7007ab3e547baf = b2sum -l 64 <<< amd-gfx120x/flash/bwd_kernel_fuse.zip;;#F;Q='*fp16:16';BLOCK_DMODEL=32;CAUSAL_TYPE=3;ENABLE_DROPOUT=True;PADDED_HEAD=False;BIAS_TYPE=0;;#P;BLOCK_M=64;BLOCK_N=32;;#CO;waves_per_eu=2;num_warps=4;num_stages=1;;arch=gfx1201
    { 0xad582e00u, 0x864da751u, 284, 244 }, // ad582e00864da751 = b2sum -l 64 <<< amd-gfx120x/flash/bwd_kernel_fuse.zip;;#F;Q='*fp16:16';BLOCK_DMODEL=32;CAUSAL_TYPE=3;ENABLE_DROPOUT=True;PADDED_HEAD=False;BIAS_TYPE=0;;#P;BLOCK_M=64;BLOCK_N=32;;#CO;waves_per_eu=3;num_warps=4;num_stages=1;;arch=gfx1201
    { 0xca4dc19fu, 0x103d66d1u, 284, 390 }, // ca4dc19f103d66d1 = b2sum -l 64 <<< amd-gfx120x/flash/bwd_kernel_fuse.zip;;#F;Q='*fp16:16';BLOCK_DMODEL=32;CAUSAL_TYPE=3;ENABLE_DROPOUT=True;PADDED_HEAD=False;BIAS_TYPE=0;;#P;BLOCK_M=64;BLOCK_N=32;;#CO;waves_per_eu=4;num_warps=4;num_stages=1;;arch=gfx1201
    { 0x26b02ddau, 0x52655331u, 306, 350 }, // 26b02dda52655331 = b2sum -l 64 <<< amd-gfx120x/flash/bwd_kernel_fuse.zip;;#F;Q='*fp16:16';BLOCK_DMODEL=32;CAUSAL_TYPE=3;ENABLE_DROPOUT=True;PADDED_HEAD=False;BIAS_TYPE=0;;#P;BLOCK_M=64;BLOCK_N=64;;#CO;waves_per_eu=1;num_warps=4;num_stages=1;;arch=gfx1201
    { 0xbaa3d25bu, 0x7d077722u, 306, 164 }, // baa3d25b7d077722 = b2sum -l 64 <<< amd-gfx120x/flash/bwd_kernel_fuse.zip;;#F;Q='*fp16:16';BLOCK_DMODEL=32;CAUSAL_TYPE=3;ENABLE_DROPOUT=True;PADDED_HEAD=False;BIAS_TYPE=0;;#P;BLOCK_M=64;BLOCK_N=64;;#CO;waves_per_eu=2;num_warps=4;num_stages=1;;arch=gfx1201
    { 0xd76b3f11u, 0x9201b126u, 306, 244 }, // d76b3f119201b126 = b2sum -l 64 <<< amd-gfx120x/flash/bwd_kernel_fuse.zip;;#F;Q='*fp16:16';BLOCK_DMODEL=32;CAUSAL_TYPE=3;ENABLE_DROPOUT=True;PADDED_HEAD=False;BIAS_TYPE=0;;#P;BLOCK_M=64;BLOCK_N=64;;#CO;waves_per_eu=3;num_warps=4;num_stages=1;;arch=gfx1201
    { 0xe6ac1db9u, 0x4b058a77u, 306, 452 }, // e6ac1db94b058a77 = b2sum -l 64 <<< amd-gfx120x/flash/bwd_kernel_fuse.zip;;#F;Q='*fp16:16';BLOCK_DMODEL=32;CAUSAL_TYPE=3;ENABLE_DROPOUT=True;PADDED_HEAD=False;BIAS_TYPE=0;;#P;BLOCK_M=64;BLOCK_N=64;;#CO;waves_per_eu=3;num_warps=8;num_stages=1;;arch=gfx1201
    { 0x720a6886u, 0x4bdabd82u, 306, 390 }, // 720a68864bdabd82 = b2sum -l 64 <<< amd-gfx120x/flash/bwd_kernel_fuse.zip;;#F;Q='*fp16:16';BLOCK_DMODEL=32;CAUSAL_TYPE=3;ENABLE_DROPOUT=True;PADDED_HEAD=False;BIAS_TYPE=0;;#P;BLOCK_M=64;BLOCK_N=64;;#CO;waves_per_eu=4;num_warps=4;num_stages=1;;arch=gfx1201
};

static constexpr int kTotalNumKernels = ARRAY_SIZE(meta_list);

using AOTRITON_NS::v3::flash::autotune::bwd_kernel_fuse_packed_string;

static AOTRITON_NS::TritonKernelCluster<kTotalNumKernels>
kernel_cluster(meta_list,
               bwd_kernel_fuse_packed_string);

static int8_t lut[1][10][10] =
{
// GPU gfx1201_mod0
{{ 3, 1, 0, 3, 2, 1, 8, 7, 6, 7},
 { 4, 4, 4, 4, 4, 8, 7, 7, 7, 6},
 { 4, 7, 5, 7, 4,11, 8, 6, 7, 7},
 { 4, 4, 6, 9, 7, 4, 6, 7, 7, 6},
 {11,11,11,11,18, 6, 6, 6, 7, 6},
 { 9, 9,11,11, 9,22,22,22,22, 6},
 {10,10,13,11, 8,21,20,21,21,21},
 { 9, 9, 9,11,15,20,20,21,21,21},
 { 9, 9,14,15,21,21,23,21,19,19},
 { 9,16,17,12,15,15,21,23,19,19}}
// End of GPU gfx1201_mod0
}
;

}; // End of anonymous namespace

namespace AOTRITON_NS::v3::flash::autotune {

// using AOTRITON_NS::v2::flash::BwdKernelFuseContext;

// Returns the selected kernel_index, or -1 when no valid kernel was selected.
// The kernel_index is logged by the caller (lookup_optimal in shim.cc) so the
// AOTRITON_LOG machinery is not duplicated across every generated autotune TU.
int CURRENT_ENTRY_PUBLIC(BwdKernelFuseContext& context, int mod_number) {
#if AOTRITON_BUILD_FOR_TUNING
    constexpr int kLutInTuningModeAlwaysReturnZero = 0;
    AOTRITON_LOG(LOG_DEBUG,
                 "Autotune_bwd_kernel_fuse__A9__F28 "
                 "kTotalNumKernels = %d _has_preferred_kernel = %d",
                 kTotalNumKernels, context._has_preferred_kernel);
#ifndef NDEBUG
    assert(bwd_kernel_fuse__lut_lambda__0(*context.params, mod_number, lut) == kLutInTuningModeAlwaysReturnZero);
#endif
    int preferred = context._has_preferred_kernel;
    int kernel_index = preferred < 0 ? kLutInTuningModeAlwaysReturnZero : preferred;
#else
    auto kernel_index = bwd_kernel_fuse__lut_lambda__0(*context.params, mod_number, lut);
#endif
    if (kernel_index < 0 || kernel_index >= kTotalNumKernels) {
        return -1;
    }
    context.kernel_on_device = kernel_cluster.get(kernel_index);
    context.pp_args_index = 5;
    context.flatzip_path = FLATZIP_PATH;
    // aks2_entry IS the func_name (supplied by f.unified_signature)
    context.aks2_entry   = FUNC_NAME;
    context.func_name = FUNC_NAME;
    context.arch_name = ARCH_NAME;
#if AOTRITON_BUILD_FOR_TUNING
    context._total_number_of_kernels = kTotalNumKernels;
    context._preferred_kernel_psels = kernel_psels[kernel_index];
    context._preferred_kernel_copts = kernel_copts[kernel_index];
#endif
    const auto& perf = image_perf_list[kernel_index];
    context.BLOCK_M = perf.BLOCK_M;
    context.BLOCK_N = perf.BLOCK_N;
    return kernel_index;
}

#undef CURRENT_ENTRY_PUBLIC
}

// Human-readable Signature 
// Q = "*fp16:16"
// sm_scale = "fp32"
// L = "*fp32:16"
// stride_bz = 0
// stride_bh = 0
// stride_bm = 0
// stride_dbz = 0
// stride_dbh = 0
// stride_dbm = 0
// num_head_q = "i32"
// cu_seqlens_q = "*i32:16"
// num_seqlens = "i32"
// dropout_p = "fp32"
// philox_seed_ptr = "*u64"
// philox_offset2 = "u64"
// Window_left = "i32"
// Window_right = "i32"
// BLOCK_DMODEL = 32
// CAUSAL_TYPE = 3
// ENABLE_DROPOUT = True
// PADDED_HEAD = False
// BIAS_TYPE = 0

// ('SELECT * FROM FLASH$bwd_kernel_fuse WHERE gpu IN (?) AND inputs$Q_dtype = ? AND inputs$BLOCK_DMODEL = ? AND inputs$CAUSAL_TYPE = ? AND inputs$ENABLE_DROPOUT = ? AND inputs$PADDED_HEAD = ? AND inputs$BIAS_TYPE = ?', ['gfx1201_mod0', 'torch.float16', 32, 3, True, False, 0])

// vim: set fileencoding=utf-8

