// Copyright © 2023-2025 Advanced Micro Devices, Inc.
// SPDX-License-Identifier: MIT

#include "../shim.bwd_kernel_dq.h"
#include <aotriton/_internal/triton_kernel.h>
#include <aotriton/_internal/kernel_cluster.h>
#include <aotriton/_internal/log.h>
#include <aotriton/cpp_tune.h>
#include <assert.h>
#include <string_view>

#define CURRENT_ENTRY_PUBLIC Autotune_bwd_kernel_dq__A6__F211

#define ARRAY_SIZE(array)  (sizeof(array) / sizeof(array[0]))

namespace { // Anonymous namespace

using namespace std::literals::string_view_literals;

#if AOTRITON_BUILD_FOR_TUNING
// PSels and Copts in JSON String
static const char* kernel_psels[] = {
  R"xyzw({"BLOCK_M": 16, "BLOCK_N": 16, "NUM_XCDS": 1})xyzw",
  R"xyzw({"BLOCK_M": 16, "BLOCK_N": 16, "NUM_XCDS": 1})xyzw",
  R"xyzw({"BLOCK_M": 16, "BLOCK_N": 16, "NUM_XCDS": 1})xyzw",
  R"xyzw({"BLOCK_M": 16, "BLOCK_N": 16, "NUM_XCDS": 1})xyzw",
  R"xyzw({"BLOCK_M": 32, "BLOCK_N": 16, "NUM_XCDS": 1})xyzw",
  R"xyzw({"BLOCK_M": 32, "BLOCK_N": 32, "NUM_XCDS": 1})xyzw",
  R"xyzw({"BLOCK_M": 32, "BLOCK_N": 32, "NUM_XCDS": 1})xyzw",
  R"xyzw({"BLOCK_M": 32, "BLOCK_N": 32, "NUM_XCDS": 1})xyzw",
  R"xyzw({"BLOCK_M": 32, "BLOCK_N": 32, "NUM_XCDS": 1})xyzw",
  R"xyzw({"BLOCK_M": 32, "BLOCK_N": 32, "NUM_XCDS": 1})xyzw",
  R"xyzw({"BLOCK_M": 32, "BLOCK_N": 32, "NUM_XCDS": 1})xyzw",
  R"xyzw({"BLOCK_M": 64, "BLOCK_N": 16, "NUM_XCDS": 1})xyzw",
  R"xyzw({"BLOCK_M": 64, "BLOCK_N": 16, "NUM_XCDS": 1})xyzw",
  R"xyzw({"BLOCK_M": 64, "BLOCK_N": 16, "NUM_XCDS": 1})xyzw",
  R"xyzw({"BLOCK_M": 64, "BLOCK_N": 16, "NUM_XCDS": 1})xyzw",
  R"xyzw({"BLOCK_M": 64, "BLOCK_N": 32, "NUM_XCDS": 1})xyzw",
  R"xyzw({"BLOCK_M": 64, "BLOCK_N": 32, "NUM_XCDS": 1})xyzw",
  R"xyzw({"BLOCK_M": 64, "BLOCK_N": 32, "NUM_XCDS": 1})xyzw",
  R"xyzw({"BLOCK_M": 64, "BLOCK_N": 32, "NUM_XCDS": 1})xyzw",
  R"xyzw({"BLOCK_M": 64, "BLOCK_N": 64, "NUM_XCDS": 1})xyzw",
  R"xyzw({"BLOCK_M": 64, "BLOCK_N": 64, "NUM_XCDS": 1})xyzw",
  R"xyzw({"BLOCK_M": 64, "BLOCK_N": 64, "NUM_XCDS": 1})xyzw",
  R"xyzw({"BLOCK_M": 64, "BLOCK_N": 64, "NUM_XCDS": 1})xyzw"
};
static const char* kernel_copts[] = {
  R"xyzw({"waves_per_eu": 1, "num_warps": 4, "num_stages": 1})xyzw",
  R"xyzw({"waves_per_eu": 2, "num_warps": 4, "num_stages": 1})xyzw",
  R"xyzw({"waves_per_eu": 3, "num_warps": 4, "num_stages": 1})xyzw",
  R"xyzw({"waves_per_eu": 4, "num_warps": 4, "num_stages": 1})xyzw",
  R"xyzw({"waves_per_eu": 2, "num_warps": 4, "num_stages": 1})xyzw",
  R"xyzw({"waves_per_eu": 1, "num_warps": 4, "num_stages": 1})xyzw",
  R"xyzw({"waves_per_eu": 1, "num_warps": 8, "num_stages": 1})xyzw",
  R"xyzw({"waves_per_eu": 2, "num_warps": 4, "num_stages": 1})xyzw",
  R"xyzw({"waves_per_eu": 3, "num_warps": 4, "num_stages": 1})xyzw",
  R"xyzw({"waves_per_eu": 4, "num_warps": 4, "num_stages": 1})xyzw",
  R"xyzw({"waves_per_eu": 4, "num_warps": 8, "num_stages": 1})xyzw",
  R"xyzw({"waves_per_eu": 1, "num_warps": 4, "num_stages": 1})xyzw",
  R"xyzw({"waves_per_eu": 2, "num_warps": 4, "num_stages": 1})xyzw",
  R"xyzw({"waves_per_eu": 3, "num_warps": 4, "num_stages": 1})xyzw",
  R"xyzw({"waves_per_eu": 4, "num_warps": 4, "num_stages": 1})xyzw",
  R"xyzw({"waves_per_eu": 1, "num_warps": 4, "num_stages": 1})xyzw",
  R"xyzw({"waves_per_eu": 2, "num_warps": 4, "num_stages": 1})xyzw",
  R"xyzw({"waves_per_eu": 3, "num_warps": 4, "num_stages": 1})xyzw",
  R"xyzw({"waves_per_eu": 4, "num_warps": 4, "num_stages": 1})xyzw",
  R"xyzw({"waves_per_eu": 1, "num_warps": 8, "num_stages": 1})xyzw",
  R"xyzw({"waves_per_eu": 2, "num_warps": 8, "num_stages": 1})xyzw",
  R"xyzw({"waves_per_eu": 3, "num_warps": 8, "num_stages": 1})xyzw",
  R"xyzw({"waves_per_eu": 4, "num_warps": 8, "num_stages": 1})xyzw"
};
#endif

struct PerfFields {
  int16_t BLOCK_M;
    int16_t BLOCK_N;
    int8_t  NUM_XCDS;
};

static PerfFields image_perf_list [] = {
    { .BLOCK_M = 16, .BLOCK_N = 16, .NUM_XCDS = 1 },
    { .BLOCK_M = 16, .BLOCK_N = 16, .NUM_XCDS = 1 },
    { .BLOCK_M = 16, .BLOCK_N = 16, .NUM_XCDS = 1 },
    { .BLOCK_M = 16, .BLOCK_N = 16, .NUM_XCDS = 1 },
    { .BLOCK_M = 32, .BLOCK_N = 16, .NUM_XCDS = 1 },
    { .BLOCK_M = 32, .BLOCK_N = 32, .NUM_XCDS = 1 },
    { .BLOCK_M = 32, .BLOCK_N = 32, .NUM_XCDS = 1 },
    { .BLOCK_M = 32, .BLOCK_N = 32, .NUM_XCDS = 1 },
    { .BLOCK_M = 32, .BLOCK_N = 32, .NUM_XCDS = 1 },
    { .BLOCK_M = 32, .BLOCK_N = 32, .NUM_XCDS = 1 },
    { .BLOCK_M = 32, .BLOCK_N = 32, .NUM_XCDS = 1 },
    { .BLOCK_M = 64, .BLOCK_N = 16, .NUM_XCDS = 1 },
    { .BLOCK_M = 64, .BLOCK_N = 16, .NUM_XCDS = 1 },
    { .BLOCK_M = 64, .BLOCK_N = 16, .NUM_XCDS = 1 },
    { .BLOCK_M = 64, .BLOCK_N = 16, .NUM_XCDS = 1 },
    { .BLOCK_M = 64, .BLOCK_N = 32, .NUM_XCDS = 1 },
    { .BLOCK_M = 64, .BLOCK_N = 32, .NUM_XCDS = 1 },
    { .BLOCK_M = 64, .BLOCK_N = 32, .NUM_XCDS = 1 },
    { .BLOCK_M = 64, .BLOCK_N = 32, .NUM_XCDS = 1 },
    { .BLOCK_M = 64, .BLOCK_N = 64, .NUM_XCDS = 1 },
    { .BLOCK_M = 64, .BLOCK_N = 64, .NUM_XCDS = 1 },
    { .BLOCK_M = 64, .BLOCK_N = 64, .NUM_XCDS = 1 },
    { .BLOCK_M = 64, .BLOCK_N = 64, .NUM_XCDS = 1 }
};

// u8R generates char8_t which is poorly supported almost everywhere.
// TODO: deduplicate FLATZIP_PATH via shim.cc packed_string
constexpr pstring_view FLATZIP_PATH
#if defined(_WIN32)
{ LR"xyzw(amd-gfx115x/flash/bwd_kernel_dq.zip)xyzw" };
#else
{ R"xyzw(amd-gfx115x/flash/bwd_kernel_dq.zip)xyzw" };
#endif
constexpr std::string_view FUNC_NAME   { R"xyzw(Q='*bf16:16';BLOCK_DMODEL=32;CAUSAL_TYPE=0;ENABLE_DROPOUT=False;PADDED_HEAD=True;BIAS_TYPE=1)xyzw"   };
constexpr std::string_view ARCH_NAME { R"xyzw(gfx1151)xyzw" };

// Checksum can be confirmed with `echo -n '<string>' | b2sum -l 64`
// For example:
//   $ echo -n 'amd-gfx110x/flash/attn_fwd/FONLY__^bf16@16,128,False,False,0,0___gfx1100__P__32_32_0_2_False__CO__wave3_warp2_stg1-Gpu-gfx1100' | b2sum -l 64
//   c4b51ee645d79580  -
static AOTRITON_NS::TritonKernelCompactMeta meta_list[] = {
    { 0x776df7a4u, 0x46400945u, 650, 292 }, // 776df7a446400945 = b2sum -l 64 <<< amd-gfx115x/flash/bwd_kernel_dq.zip;;#F;Q='*bf16:16';BLOCK_DMODEL=32;CAUSAL_TYPE=0;ENABLE_DROPOUT=False;PADDED_HEAD=True;BIAS_TYPE=1;;#P;BLOCK_M=16;BLOCK_N=16;NUM_XCDS=1;;#CO;waves_per_eu=1;num_warps=4;num_stages=1;;arch=gfx1151
    { 0x7b356812u, 0xb6538b9eu, 650, 398 }, // 7b356812b6538b9e = b2sum -l 64 <<< amd-gfx115x/flash/bwd_kernel_dq.zip;;#F;Q='*bf16:16';BLOCK_DMODEL=32;CAUSAL_TYPE=0;ENABLE_DROPOUT=False;PADDED_HEAD=True;BIAS_TYPE=1;;#P;BLOCK_M=16;BLOCK_N=16;NUM_XCDS=1;;#CO;waves_per_eu=2;num_warps=4;num_stages=1;;arch=gfx1151
    { 0xb5b4ec5du, 0x86a60e20u, 650, 478 }, // b5b4ec5d86a60e20 = b2sum -l 64 <<< amd-gfx115x/flash/bwd_kernel_dq.zip;;#F;Q='*bf16:16';BLOCK_DMODEL=32;CAUSAL_TYPE=0;ENABLE_DROPOUT=False;PADDED_HEAD=True;BIAS_TYPE=1;;#P;BLOCK_M=16;BLOCK_N=16;NUM_XCDS=1;;#CO;waves_per_eu=3;num_warps=4;num_stages=1;;arch=gfx1151
    { 0x3a73ea21u, 0x7b403df7u, 650, 438 }, // 3a73ea217b403df7 = b2sum -l 64 <<< amd-gfx115x/flash/bwd_kernel_dq.zip;;#F;Q='*bf16:16';BLOCK_DMODEL=32;CAUSAL_TYPE=0;ENABLE_DROPOUT=False;PADDED_HEAD=True;BIAS_TYPE=1;;#P;BLOCK_M=16;BLOCK_N=16;NUM_XCDS=1;;#CO;waves_per_eu=4;num_warps=4;num_stages=1;;arch=gfx1151
    { 0x0facffabu, 0x4cdfa829u, 843, 398 }, // 0facffab4cdfa829 = b2sum -l 64 <<< amd-gfx115x/flash/bwd_kernel_dq.zip;;#F;Q='*bf16:16';BLOCK_DMODEL=32;CAUSAL_TYPE=0;ENABLE_DROPOUT=False;PADDED_HEAD=True;BIAS_TYPE=1;;#P;BLOCK_M=32;BLOCK_N=16;NUM_XCDS=1;;#CO;waves_per_eu=2;num_warps=4;num_stages=1;;arch=gfx1151
    { 0x85eb7d07u, 0x56efd660u, 518, 292 }, // 85eb7d0756efd660 = b2sum -l 64 <<< amd-gfx115x/flash/bwd_kernel_dq.zip;;#F;Q='*bf16:16';BLOCK_DMODEL=32;CAUSAL_TYPE=0;ENABLE_DROPOUT=False;PADDED_HEAD=True;BIAS_TYPE=1;;#P;BLOCK_M=32;BLOCK_N=32;NUM_XCDS=1;;#CO;waves_per_eu=1;num_warps=4;num_stages=1;;arch=gfx1151
    { 0xda72bb9du, 0xaddb1ebdu, 518, 683 }, // da72bb9daddb1ebd = b2sum -l 64 <<< amd-gfx115x/flash/bwd_kernel_dq.zip;;#F;Q='*bf16:16';BLOCK_DMODEL=32;CAUSAL_TYPE=0;ENABLE_DROPOUT=False;PADDED_HEAD=True;BIAS_TYPE=1;;#P;BLOCK_M=32;BLOCK_N=32;NUM_XCDS=1;;#CO;waves_per_eu=1;num_warps=8;num_stages=1;;arch=gfx1151
    { 0x7dd23e45u, 0x444330f6u, 518, 398 }, // 7dd23e45444330f6 = b2sum -l 64 <<< amd-gfx115x/flash/bwd_kernel_dq.zip;;#F;Q='*bf16:16';BLOCK_DMODEL=32;CAUSAL_TYPE=0;ENABLE_DROPOUT=False;PADDED_HEAD=True;BIAS_TYPE=1;;#P;BLOCK_M=32;BLOCK_N=32;NUM_XCDS=1;;#CO;waves_per_eu=2;num_warps=4;num_stages=1;;arch=gfx1151
    { 0x831c549au, 0x309fc4b8u, 518, 478 }, // 831c549a309fc4b8 = b2sum -l 64 <<< amd-gfx115x/flash/bwd_kernel_dq.zip;;#F;Q='*bf16:16';BLOCK_DMODEL=32;CAUSAL_TYPE=0;ENABLE_DROPOUT=False;PADDED_HEAD=True;BIAS_TYPE=1;;#P;BLOCK_M=32;BLOCK_N=32;NUM_XCDS=1;;#CO;waves_per_eu=3;num_warps=4;num_stages=1;;arch=gfx1151
    { 0xd407b8c0u, 0x5b4f4da9u, 518, 438 }, // d407b8c05b4f4da9 = b2sum -l 64 <<< amd-gfx115x/flash/bwd_kernel_dq.zip;;#F;Q='*bf16:16';BLOCK_DMODEL=32;CAUSAL_TYPE=0;ENABLE_DROPOUT=False;PADDED_HEAD=True;BIAS_TYPE=1;;#P;BLOCK_M=32;BLOCK_N=32;NUM_XCDS=1;;#CO;waves_per_eu=4;num_warps=4;num_stages=1;;arch=gfx1151
    { 0xd7971bd6u, 0xc558ec1cu, 518, 803 }, // d7971bd6c558ec1c = b2sum -l 64 <<< amd-gfx115x/flash/bwd_kernel_dq.zip;;#F;Q='*bf16:16';BLOCK_DMODEL=32;CAUSAL_TYPE=0;ENABLE_DROPOUT=False;PADDED_HEAD=True;BIAS_TYPE=1;;#P;BLOCK_M=32;BLOCK_N=32;NUM_XCDS=1;;#CO;waves_per_eu=4;num_warps=8;num_stages=1;;arch=gfx1151
    { 0x7253a666u, 0x28a00ad6u, 551, 292 }, // 7253a66628a00ad6 = b2sum -l 64 <<< amd-gfx115x/flash/bwd_kernel_dq.zip;;#F;Q='*bf16:16';BLOCK_DMODEL=32;CAUSAL_TYPE=0;ENABLE_DROPOUT=False;PADDED_HEAD=True;BIAS_TYPE=1;;#P;BLOCK_M=64;BLOCK_N=16;NUM_XCDS=1;;#CO;waves_per_eu=1;num_warps=4;num_stages=1;;arch=gfx1151
    { 0xc7808b3du, 0xae4292d8u, 551, 398 }, // c7808b3dae4292d8 = b2sum -l 64 <<< amd-gfx115x/flash/bwd_kernel_dq.zip;;#F;Q='*bf16:16';BLOCK_DMODEL=32;CAUSAL_TYPE=0;ENABLE_DROPOUT=False;PADDED_HEAD=True;BIAS_TYPE=1;;#P;BLOCK_M=64;BLOCK_N=16;NUM_XCDS=1;;#CO;waves_per_eu=2;num_warps=4;num_stages=1;;arch=gfx1151
    { 0xda6e25f5u, 0xd60f106fu, 551, 478 }, // da6e25f5d60f106f = b2sum -l 64 <<< amd-gfx115x/flash/bwd_kernel_dq.zip;;#F;Q='*bf16:16';BLOCK_DMODEL=32;CAUSAL_TYPE=0;ENABLE_DROPOUT=False;PADDED_HEAD=True;BIAS_TYPE=1;;#P;BLOCK_M=64;BLOCK_N=16;NUM_XCDS=1;;#CO;waves_per_eu=3;num_warps=4;num_stages=1;;arch=gfx1151
    { 0xc02dec4du, 0xc593c835u, 551, 438 }, // c02dec4dc593c835 = b2sum -l 64 <<< amd-gfx115x/flash/bwd_kernel_dq.zip;;#F;Q='*bf16:16';BLOCK_DMODEL=32;CAUSAL_TYPE=0;ENABLE_DROPOUT=False;PADDED_HEAD=True;BIAS_TYPE=1;;#P;BLOCK_M=64;BLOCK_N=16;NUM_XCDS=1;;#CO;waves_per_eu=4;num_warps=4;num_stages=1;;arch=gfx1151
    { 0x8ad20ecfu, 0x87b2d293u, 584, 292 }, // 8ad20ecf87b2d293 = b2sum -l 64 <<< amd-gfx115x/flash/bwd_kernel_dq.zip;;#F;Q='*bf16:16';BLOCK_DMODEL=32;CAUSAL_TYPE=0;ENABLE_DROPOUT=False;PADDED_HEAD=True;BIAS_TYPE=1;;#P;BLOCK_M=64;BLOCK_N=32;NUM_XCDS=1;;#CO;waves_per_eu=1;num_warps=4;num_stages=1;;arch=gfx1151
    { 0xdaa67d71u, 0x3cfa535fu, 584, 398 }, // daa67d713cfa535f = b2sum -l 64 <<< amd-gfx115x/flash/bwd_kernel_dq.zip;;#F;Q='*bf16:16';BLOCK_DMODEL=32;CAUSAL_TYPE=0;ENABLE_DROPOUT=False;PADDED_HEAD=True;BIAS_TYPE=1;;#P;BLOCK_M=64;BLOCK_N=32;NUM_XCDS=1;;#CO;waves_per_eu=2;num_warps=4;num_stages=1;;arch=gfx1151
    { 0x3e98b717u, 0xf9bc5617u, 584, 478 }, // 3e98b717f9bc5617 = b2sum -l 64 <<< amd-gfx115x/flash/bwd_kernel_dq.zip;;#F;Q='*bf16:16';BLOCK_DMODEL=32;CAUSAL_TYPE=0;ENABLE_DROPOUT=False;PADDED_HEAD=True;BIAS_TYPE=1;;#P;BLOCK_M=64;BLOCK_N=32;NUM_XCDS=1;;#CO;waves_per_eu=3;num_warps=4;num_stages=1;;arch=gfx1151
    { 0x4f10e499u, 0xe3588c91u, 584, 438 }, // 4f10e499e3588c91 = b2sum -l 64 <<< amd-gfx115x/flash/bwd_kernel_dq.zip;;#F;Q='*bf16:16';BLOCK_DMODEL=32;CAUSAL_TYPE=0;ENABLE_DROPOUT=False;PADDED_HEAD=True;BIAS_TYPE=1;;#P;BLOCK_M=64;BLOCK_N=32;NUM_XCDS=1;;#CO;waves_per_eu=4;num_warps=4;num_stages=1;;arch=gfx1151
    { 0xd4cac23fu, 0x47f99424u, 617, 683 }, // d4cac23f47f99424 = b2sum -l 64 <<< amd-gfx115x/flash/bwd_kernel_dq.zip;;#F;Q='*bf16:16';BLOCK_DMODEL=32;CAUSAL_TYPE=0;ENABLE_DROPOUT=False;PADDED_HEAD=True;BIAS_TYPE=1;;#P;BLOCK_M=64;BLOCK_N=64;NUM_XCDS=1;;#CO;waves_per_eu=1;num_warps=8;num_stages=1;;arch=gfx1151
    { 0xb0747688u, 0x50df0f80u, 617, 723 }, // b074768850df0f80 = b2sum -l 64 <<< amd-gfx115x/flash/bwd_kernel_dq.zip;;#F;Q='*bf16:16';BLOCK_DMODEL=32;CAUSAL_TYPE=0;ENABLE_DROPOUT=False;PADDED_HEAD=True;BIAS_TYPE=1;;#P;BLOCK_M=64;BLOCK_N=64;NUM_XCDS=1;;#CO;waves_per_eu=2;num_warps=8;num_stages=1;;arch=gfx1151
    { 0xe0881c21u, 0xdd2d4b93u, 617, 763 }, // e0881c21dd2d4b93 = b2sum -l 64 <<< amd-gfx115x/flash/bwd_kernel_dq.zip;;#F;Q='*bf16:16';BLOCK_DMODEL=32;CAUSAL_TYPE=0;ENABLE_DROPOUT=False;PADDED_HEAD=True;BIAS_TYPE=1;;#P;BLOCK_M=64;BLOCK_N=64;NUM_XCDS=1;;#CO;waves_per_eu=3;num_warps=8;num_stages=1;;arch=gfx1151
    { 0x7612b429u, 0x6f86449cu, 617, 803 }, // 7612b4296f86449c = b2sum -l 64 <<< amd-gfx115x/flash/bwd_kernel_dq.zip;;#F;Q='*bf16:16';BLOCK_DMODEL=32;CAUSAL_TYPE=0;ENABLE_DROPOUT=False;PADDED_HEAD=True;BIAS_TYPE=1;;#P;BLOCK_M=64;BLOCK_N=64;NUM_XCDS=1;;#CO;waves_per_eu=4;num_warps=8;num_stages=1;;arch=gfx1151
};

static constexpr int kTotalNumKernels = ARRAY_SIZE(meta_list);

using AOTRITON_NS::v3::flash::autotune::bwd_kernel_dq_packed_string;

static AOTRITON_NS::TritonKernelCluster<kTotalNumKernels>
kernel_cluster(meta_list,
               bwd_kernel_dq_packed_string);

static int8_t lut[1][8][8] =
{
// GPU gfx1151_mod0
{{ 4, 7,22,20,20,21,20,19},
 {13,17,19,20,22, 9, 5, 7},
 { 3, 7,18,16, 5, 5, 8, 9},
 { 0, 0,17, 7,16, 9, 9, 8},
 { 1, 2, 8, 5, 8, 8, 5, 9},
 {11,11,17,18,16, 8, 5,10},
 {14,11,11,13, 7, 8,22,21},
 {13,12,12,17,15, 6,22,22}}
// End of GPU gfx1151_mod0
}
;

}; // End of anonymous namespace

namespace AOTRITON_NS::v3::flash::autotune {

// using AOTRITON_NS::v2::flash::BwdKernelDqContext;

// Returns the selected kernel_index, or -1 when no valid kernel was selected.
// The kernel_index is logged by the caller (lookup_optimal in shim.cc) so the
// AOTRITON_LOG machinery is not duplicated across every generated autotune TU.
int CURRENT_ENTRY_PUBLIC(BwdKernelDqContext& context, int mod_number) {
#if AOTRITON_BUILD_FOR_TUNING
    constexpr int kLutInTuningModeAlwaysReturnZero = 0;
    AOTRITON_LOG(LOG_DEBUG,
                 "Autotune_bwd_kernel_dq__A6__F211 "
                 "kTotalNumKernels = %d _has_preferred_kernel = %d",
                 kTotalNumKernels, context._has_preferred_kernel);
#ifndef NDEBUG
    assert(bwd_kernel_dq__lut_lambda__1(*context.params, mod_number, lut) == kLutInTuningModeAlwaysReturnZero);
#endif
    int preferred = context._has_preferred_kernel;
    int kernel_index = preferred < 0 ? kLutInTuningModeAlwaysReturnZero : preferred;
#else
    auto kernel_index = bwd_kernel_dq__lut_lambda__1(*context.params, mod_number, lut);
#endif
    if (kernel_index < 0 || kernel_index >= kTotalNumKernels) {
        return -1;
    }
    context.kernel_on_device = kernel_cluster.get(kernel_index);
    context.pp_args_index = 1;
    context.flatzip_path = FLATZIP_PATH;
    // aks2_entry IS the func_name (supplied by f.unified_signature)
    context.aks2_entry   = FUNC_NAME;
    context.func_name = FUNC_NAME;
    context.arch_name = ARCH_NAME;
#if AOTRITON_BUILD_FOR_TUNING
    context._total_number_of_kernels = kTotalNumKernels;
    context._preferred_kernel_psels = kernel_psels[kernel_index];
    context._preferred_kernel_copts = kernel_copts[kernel_index];
#endif
    const auto& perf = image_perf_list[kernel_index];
    context.BLOCK_M = perf.BLOCK_M;
    context.BLOCK_N = perf.BLOCK_N;
    context.NUM_XCDS = perf.NUM_XCDS;
    return kernel_index;
}

#undef CURRENT_ENTRY_PUBLIC
}

// Human-readable Signature 
// Q = "*bf16:16"
// sm_scale = "fp32"
// L = "*fp32:16"
// D = "*fp32:16"
// num_head_q = "i32"
// cu_seqlens_q = "*i32:16"
// num_seqlens = "i32"
// dropout_p = 0
// philox_seed_ptr = 0
// philox_offset2 = 0
// Window_left = 0
// Window_right = 0
// BLOCK_DMODEL = 32
// CAUSAL_TYPE = 0
// ENABLE_DROPOUT = False
// PADDED_HEAD = True
// BIAS_TYPE = 1

// ('SELECT * FROM FLASH$bwd_kernel_dq WHERE gpu IN (?) AND inputs$Q_dtype = ? AND inputs$BLOCK_DMODEL = ? AND inputs$CAUSAL_TYPE = ? AND inputs$ENABLE_DROPOUT = ? AND inputs$PADDED_HEAD = ? AND inputs$BIAS_TYPE = ?', ['gfx1100_mod0', 'torch.bfloat16', 32, 0, False, False, 1])

// vim: set fileencoding=utf-8

