GTPin
Public Member Functions
gtpin::IGtInsFactory Class Reference
GEN Instruction

Class that defines virtual constructors of IGtIns objects representing various GEN instructions. More...

#include <igt_ins_factory.h>

Public Member Functions

virtual IGtIns & Make (const ged_ins_t &gedIns)=0
 Given a GED instruction representation, create the corsponding IGtIns instance.
virtual IGtIns & Make (const IGtIns &ins)=0
 Create a copy of the specified instruction.
virtual IGtIns & MakeOpRR (GtOpcode op, const GtDstRegion &dst, const GtRegRegion &src0, GtExecMask execMask={1})=0
 Construct a common (arithmetic, logic) 1-source instruction: op(execMask) dst<Reg> src0<Reg>
virtual IGtIns & MakeOpRI (GtOpcode op, const GtDstRegion &dst, const GtImm &src0, GtExecMask execMask={1})=0
 Construct a common (arithmetic, logic) 1-source instruction: op(execMask) dst<Reg> src0<Imm>
virtual IGtIns & MakeOpRRR (GtOpcode op, const GtDstRegion &dst, const GtRegRegion &src0, const GtRegRegion &src1, GtExecMask execMask={1})=0
 Construct a common (arithmetic, logic) 2-source instruction: op(execMask) dst<Reg> src0<Reg> src1<Reg>
virtual IGtIns & MakeOpRRI (GtOpcode op, const GtDstRegion &dst, const GtRegRegion &src0, const GtImm &src1, GtExecMask execMask={1})=0
 Construct a common (arithmetic, logic) 2-source instruction: op(execMask) dst<Reg> src0<Reg> src1<Imm>
virtual IGtIns & MakeOp3Src (GtOpcode op, const GtDstRegion &dst, const GtRegRegion &src0, const GtRegRegion &src1, const GtRegRegion &src2, GtExecMask execMask={1})=0
 Construct a common 3-source instruction: op(execMask) dst<Reg> src0<Reg> src1<Reg> src2<Reg>
virtual IGtIns & MakeRegMov (const GtReg &dst, const GtReg &src0)=0
 Construct an instruction that moves all bytes of src0 to dst.
virtual IGtIns & MakeRegZero (const GtReg &reg)=0
 Construct an instruction that sets zero value in all bytes of the specified register.
virtual IGtIns & MakeCmp (GtCondModifier cond, const GtReg &flagReg, const GtRegRegion &src0, const GtRegRegion &src1, GtExecMask execMask={1})=0
 Construct a CMP instruction: cmp(execMask) cond.flag null src0<Reg> src1<Reg>
virtual IGtIns & MakeCmp (GtCondModifier cond, const GtReg &flagReg, const GtRegRegion &src0, const GtImm &src1, GtExecMask execMask={1})=0
 Construct a CMP instruction: cmp(execMask) cond.flag null src0<Reg> src1<Imm>
virtual IGtIns & MakeIllegal ()=0
 Construct an illegal GEN instruction.
virtual IGtIns & MakeNop ()=0
 Construct a NOP instruction.
virtual IGtIns & MakeSendMsg (const GtReg &dst, const GtReg &src0, const GtReg &src1, uint32_t exDesc, uint32_t desc, GtExecMask execMask={1})=0
 Construct a SendMessage instruction: send (execMask) dst<Reg> src0<Reg> src1<Reg> exDesc<Imm>, desc<Imm>
virtual IGtIns & MakeAtomicOp (GtAtomicOp aop, const GtReg &dst, const GtReg &addrReg, const GtReg &src, GtDataType dataType, GtExecMask execMask={1})=0
 Construct instruction that atomically accesses data in the profile buffer.
virtual bool CanAccessAtomically (GtDataType dataType) const =0
 Return true, if data of the specified type can be accessed atomically in the platform associated with this factory.
virtual const IGtGenModel & GenModel () const =0
 Return GEN model of instructions created by this factory.
IGtIns & MakeMov (const GtDstRegion &dst, const GtRegRegion &src0, GtExecMask execMask={1})
 Make MOV instruction.
IGtIns & MakeMov (const GtDstRegion &dst, const GtImm &src0, GtExecMask execMask={1})
 Make MOV instruction.
IGtIns & MakeNot (const GtDstRegion &dst, const GtRegRegion &src0, GtExecMask execMask={1})
 Make NOT instruction.
IGtIns & MakeNot (const GtDstRegion &dst, const GtImm &src0, GtExecMask execMask={1})
 Make NOT instruction.
IGtIns & MakeCbit (const GtDstRegion &dst, const GtRegRegion &src0, GtExecMask execMask={1})
 Make CBIT instruction.
IGtIns & MakeCbit (const GtDstRegion &dst, const GtImm &src0, GtExecMask execMask={1})
 Make CBIT instruction.
IGtIns & MakeAdd (const GtDstRegion &dst, const GtRegRegion &src0, const GtRegRegion &src1, GtExecMask execMask={1})
 Make ADD instruction.
IGtIns & MakeAdd (const GtDstRegion &dst, const GtRegRegion &src0, const GtImm &src1, GtExecMask execMask={1})
 Make ADD instruction.
IGtIns & MakeAddc (const GtDstRegion &dst, const GtRegRegion &src0, const GtRegRegion &src1, GtExecMask execMask={1})
 Make ADDC instruction.
IGtIns & MakeAddc (const GtDstRegion &dst, const GtRegRegion &src0, const GtImm &src1, GtExecMask execMask={1})
 Make ADDC instruction.
IGtIns & MakeAnd (const GtDstRegion &dst, const GtRegRegion &src0, const GtRegRegion &src1, GtExecMask execMask={1})
 Make AND instruction.
IGtIns & MakeAnd (const GtDstRegion &dst, const GtRegRegion &src0, const GtImm &src1, GtExecMask execMask={1})
 Make AND instruction.
IGtIns & MakeOr (const GtDstRegion &dst, const GtRegRegion &src0, const GtRegRegion &src1, GtExecMask execMask={1})
 Make OR instruction.
IGtIns & MakeOr (const GtDstRegion &dst, const GtRegRegion &src0, const GtImm &src1, GtExecMask execMask={1})
 Make OR instruction.
IGtIns & MakeXor (const GtDstRegion &dst, const GtRegRegion &src0, const GtRegRegion &src1, GtExecMask execMask={1})
 Make XOR instruction.
IGtIns & MakeXor (const GtDstRegion &dst, const GtRegRegion &src0, const GtImm &src1, GtExecMask execMask={1})
 Make XOR instruction.
IGtIns & MakeShr (const GtDstRegion &dst, const GtRegRegion &src0, const GtRegRegion &src1, GtExecMask execMask={1})
 Make SHR instruction.
IGtIns & MakeShr (const GtDstRegion &dst, const GtRegRegion &src0, const GtImm &src1, GtExecMask execMask={1})
 Make SHR instruction.
IGtIns & MakeShl (const GtDstRegion &dst, const GtRegRegion &src0, const GtRegRegion &src1, GtExecMask execMask={1})
 Make SHL instruction.
IGtIns & MakeShl (const GtDstRegion &dst, const GtRegRegion &src0, const GtImm &src1, GtExecMask execMask={1})
 Make SHL instruction.
IGtIns & MakeMul (const GtDstRegion &dst, const GtRegRegion &src0, const GtRegRegion &src1, GtExecMask execMask={1})
 Make MUL instruction.
IGtIns & MakeMul (const GtDstRegion &dst, const GtRegRegion &src0, const GtImm &src1, GtExecMask execMask={1})
 Make MUL instruction.
IGtIns & MakeSel (const GtDstRegion &dst, const GtRegRegion &src0, const GtRegRegion &src1, GtExecMask execMask={1})
 Make SEL instruction.
IGtIns & MakeSel (const GtDstRegion &dst, const GtRegRegion &src0, const GtImm &src1, GtExecMask execMask={1})
 Make SEL instruction.
IGtIns & MakeSub (const GtDstRegion &dst, const GtRegRegion &src0, const GtRegRegion &src1, GtExecMask execMask={1})
 Make SUB instruction.
IGtIns & MakeSub (const GtDstRegion &dst, const GtRegRegion &src0, const GtImm &src1, GtExecMask execMask={1})
 Make SUB instruction.
IGtIns & MakeCsel (const GtDstRegion &dst, const GtRegRegion &src0, const GtRegRegion &src1, const GtRegRegion &src2, GtExecMask execMask={1})
 Make CSEL instruction.
IGtIns & MakeAtomicInc (const GtReg &dst, const GtReg &addrReg, GtDataType dataType=GED_DATA_TYPE_ud, GtExecMask execMask={1})
 Construct instruction that atomically increments the [addrReg] value in the profile buffer.
IGtIns & MakeAtomicDec (const GtReg &dst, const GtReg &addrReg, GtDataType dataType=GED_DATA_TYPE_ud, GtExecMask execMask={1})
 Construct instruction that atomically decrements the [addrReg] value in the profile buffer.
IGtIns & MakeAtomicAnd (const GtReg &dst, const GtReg &addrReg, const GtReg &src, GtDataType dataType=GED_DATA_TYPE_ud, GtExecMask execMask={1})
 Construct instruction that atomically stores the bitwise AND of 'src' value and [addrReg] value in the profile buffer.
IGtIns & MakeAtomicOr (const GtReg &dst, const GtReg &addrReg, const GtReg &src, GtDataType dataType=GED_DATA_TYPE_ud, GtExecMask execMask={1})
 Construct instruction that atomically stores the bitwise OR of 'src' value and [addrReg] value in the profile buffer.
IGtIns & MakeAtomicXor (const GtReg &dst, const GtReg &addrReg, const GtReg &src, GtDataType dataType=GED_DATA_TYPE_ud, GtExecMask execMask={1})
 Construct instruction that atomically stores the bitwise XOR of 'src' value and [addrReg] value in the profile buffer.
IGtIns & MakeAtomicAdd (const GtReg &dst, const GtReg &addrReg, const GtReg &src, GtDataType dataType=GED_DATA_TYPE_ud, GtExecMask execMask={1})
 Construct instruction that atomically adds 'src' value to the [addrReg] value in the profile buffer.
IGtIns & MakeAtomicSub (const GtReg &dst, const GtReg &addrReg, const GtReg &src, GtDataType dataType=GED_DATA_TYPE_ud, GtExecMask execMask={1})
 Construct instruction that atomically substracts 'src' value from the [addrReg] value in the profile buffer.
IGtIns & MakeAtomicImax (const GtReg &dst, const GtReg &addrReg, const GtReg &src, GtDataType dataType=GED_DATA_TYPE_ud, GtExecMask execMask={1})
 Construct instruction that atomically stores the signed MAX of 'src' value and the [addrReg] value in the profile buffer.
IGtIns & MakeAtomicImin (const GtReg &dst, const GtReg &addrReg, const GtReg &src, GtDataType dataType=GED_DATA_TYPE_ud, GtExecMask execMask={1})
 Construct instruction that atomically stores the signed MIN of 'src' value and the [addrReg] value in the profile buffer.
IGtIns & MakeAtomicUmax (const GtReg &dst, const GtReg &addrReg, const GtReg &src, GtDataType dataType=GED_DATA_TYPE_ud, GtExecMask execMask={1})
 Construct instruction that atomically stores the unsigned MAX of 'src' value and the [addrReg] value in the profile buffer.
IGtIns & MakeAtomicUmin (const GtReg &dst, const GtReg &addrReg, const GtReg &src, GtDataType dataType=GED_DATA_TYPE_ud, GtExecMask execMask={1})
 Construct instruction that atomically stores the unsigned MIN of 'src' value and the [addrReg] value in the profile buffer.
IGtIns & MakeAtomicXchg (const GtReg &dst, const GtReg &addrReg, const GtReg &src, GtDataType dataType=GED_DATA_TYPE_ud, GtExecMask execMask={1})
 Construct instruction that atomically exchanges 'src' value with the [addrReg] value in the profile buffer.
IGtIns & MakeAtomicStore (const GtReg &addrReg, const GtReg &src, GtDataType dataType=GED_DATA_TYPE_ud, GtExecMask execMask={1})
 Construct instruction that atomically stores 'src' value at the [addrReg] location in the profile buffer.

Detailed Description

Class that defines virtual constructors of IGtIns objects representing various GEN instructions.

GTPin tools mainly use IGtInsFactory interface to make instructions for instrumentation procedures. They receive the IGtGenCoder object along with the IGtKernelInstrument object when GTPin invokes the IGtTool::OnKernelBuild function (

See also:
IGtKernelInstrument::Coder().InstructionFactory()).
Availability:

Member Function Documentation

virtual IGtIns& gtpin::IGtInsFactory::MakeAtomicOp ( GtAtomicOp  aop,
const GtReg &  dst,
const GtReg &  addrReg,
const GtReg &  src,
GtDataType  dataType 
) [pure virtual]

Construct instruction that atomically accesses data in the profile buffer.

Parameters:
[in]aopOpcode of the atomic operation
[in]dstRegister that receives output of the atomic operation. NullReg() indicates that no output data is requested
[in]addrRegRegister that specifies address of data within profile buffer to be modified by the atomic operation.
[in]srcRegister that holds the input data of the atomic operation, or NullReg() if this operation has no sources
[in]dataTypeType of the SIMD data element the instruction operates on. 32-bit integers (GED_DATA_TYPE_ud) are supported in all platforms. For any other type, check CanAccessAtomically(dataType).
[in]execMaskSpecifies SIMD data elements to be accesed by the instruction. Indirectly, this paramter also specifies the total data size.
Precondition:
addrReg, dst, and src registers are zero-aligned: GtReg::SubRegNum() == 0 for physical register, and IGtVreg::RequiredSubregNum() == 0 for virtual register. Virtual registers created by IGtVregFactory::MakeMsgAddrScratch() and IGtVregFactory::MakeMsgDataScratch() satisfy this requirement.
virtual IGtIns& gtpin::IGtInsFactory::MakeRegMov ( const GtReg &  dst,
const GtReg &  src0 
) [pure virtual]

Construct an instruction that moves all bytes of src0 to dst.

Precondition:
dst.ElementSize() == src0.ElementSize()
virtual IGtIns& gtpin::IGtInsFactory::MakeSendMsg ( const GtReg &  dst,
const GtReg &  src0,
const GtReg &  src1,
uint32_t  exDesc,
uint32_t  desc 
) [pure virtual]

Construct a SendMessage instruction: send (execMask) dst<Reg> src0<Reg> src1<Reg> exDesc<Imm>, desc<Imm>

Note:
This function ignores GtReg::SubRegNum() and GtReg::ElementSize() in the operands specifications.
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  SPDX-License-Identifier: MIT
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