GTPin: GEN Architecture

Classes that represent various GEN architecture elements and expose properties of specific GEN models More...

Data Structures
class	gtpin::GtGenModelId
	The GEN model identifier. More...
class	gtpin::GtMemoryAddrModel
	Class that represents Address Model of the memory surface access. More...
class	gtpin::GtAddrSpace
	Logically distinct address spaces in GFX runtime (OpenCL, Level-Zero, etc.) More...
struct	gtpin::GtStateRegAccessor
	Structure that defines some fields of the GEN State Register (SR) and provides access to these fields. More...
class	gtpin::GtSimdWidth
	SIMD width. More...
class	gtpin::GtGpuPlatform
	GPU platform. More...
class	gtpin::GtBinaryFormat
	Format of a binary GFX program module. More...
class	gtpin::GtAccessType
	Type of access to memory region, register, etc. More...
class	gtpin::GtMemoryAccessChannelType
	Type of access to memory with XYZW channels. More...
struct	gtpin::GtMemoryBuffer
	Memory buffer in the virtual address space of the device. More...
union	gtpin::GtKernelExecDesc
	Kernel execution descriptor. More...
class	gtpin::GtOpcode
	An attribute that specifies whether and how the instruction modifies flag register. More...
class	gtpin::GtCondModifier
	An attribute that specifies whether and how the instruction modifies flag register. More...
class	gtpin::GtAddrMode
	Addressing mode of the instruction operand. More...
class	gtpin::GtSrcModifier
	Modifier of the source operand. More...
class	gtpin::GtThreadCtrl
	Instruction attribute that controls thread switching. More...
class	gtpin::GtPredCtrl
	An attribute that specifies whether and how the instruction is predicated. More...
class	gtpin::GtPredicate
	Arguments of the GEN Predicate Mask calculator. More...
class	gtpin::GtExecSize
	Execution size of the instruction. More...
class	gtpin::GtChannelOffset
	Offset of the execution (channel) mask. More...
class	gtpin::GtExecMask
	Execution mask of the instruction. More...
class	gtpin::GtSfid
	Shared Function ID. More...
class	gtpin::GtMathFC
	Math Function Control. More...
class	gtpin::GtMessageType
	SEND message type. More...
class	gtpin::GtAtomicOp
	Type of the atomic operation. More...
class	gtpin::GtDataType
	Data type of the instruction operand. More...
struct	gtpin::GtStride
	Structure that specifies striding scheme of the register region. More...
class	gtpin::GtRegRegion
	Register operand of the GEN instruction. Defines the register region accessed by the instruction. More...
class	gtpin::GtDstRegion
	Destination operand of the GEN instruction. More...
class	gtpin::GtImm
	Immediate operand of the GEN instruction. More...
class	gtpin::GtSystolicInfo
	Properties/attributes of the systolic array instruction. More...
class	gtpin::IGtGenModel
	Basic properties of the GEN model. More...
class	gtpin::IGtGenArch
	Abstract singleton that provides access to generic and model-specific properties of the GEN architecture. More...
Modules
	GEN Register
	Types that represent GEN registers and their elements
	GEN Instruction
	A group of GEN instruction inspection interfaces
Enumerations
enum	gtpin::SIMD_WIDTH { ,   gtpin::SIMD_WIDTH_1 = 1,   gtpin::SIMD_WIDTH_4x2 = 4,   gtpin::SIMD_WIDTH_8 = 8,   gtpin::SIMD_WIDTH_16 = 16,   gtpin::SIMD_WIDTH_32 = 32 }
	SIMD width. More...
enum	gtpin::GPU_PLATFORM { ,   gtpin::GPU_PLATFORM_OCL,   gtpin::GPU_PLATFORM_DX11,   gtpin::GPU_PLATFORM_DX12,   gtpin::GPU_PLATFORM_VULKAN,   gtpin::GPU_PLATFORM_L0 }
	GPU platform. More...
enum	gtpin::GT_ACCESS_TYPE {   gtpin::GT_ACCESS_NONE = 0,   gtpin::GT_ACCESS_READ = 0x1,   gtpin::GT_ACCESS_WRITE = 0x2,   gtpin::GT_ACCESS_READ_WRITE = (uint32_t(GT_ACCESS_READ) | uint32_t(GT_ACCESS_WRITE)) }
	Bit flags that represent types of accesses to memory regions, registers, etc. Any combination of these flags is a valid access type. More...
enum	gtpin::GT_MEM_ACCESS_CHANNEL_TYPE
	Bit flags that represent types of accesses to memory with XYZW channels. Specifies which components of the data payload 4-element vector (X,Y,Z,W) is packed into the register payload. Any combination of none zero flags is a valid access type.
Functions
GtStride	gtpin::ScalarStride ()
	Return striding scheme for scalar register region.
GtRegRegion	gtpin::ScalarRegion (const GtReg &reg, GtDataType dataType)
	Construct a scalar register region with the specified origin and element type.
constexpr GtImm	gtpin::GtImmU32 (uint32_t value)
	Construct immediate operand of GED_DATA_TYPE_ud type (unsigned 32-bit integer)
constexpr GtImm	gtpin::GtImmS32 (int32_t value)
	Construct immediate operand of GED_DATA_TYPE_d type (signed 32-bit integer)
const IGtGenArch &	gtpin::GetGenArch ()
	Return single instance of the IGtGenArch class.
const IGtGenModel &	gtpin::GetGenModel (GtGenModelId id)
	Return object that provides access to basic properties of the specified GEN model.

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Detailed Description

Classes that represent various GEN architecture elements and expose properties of specific GEN models

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Enumeration Type Documentation

enum gtpin::GPU_PLATFORM

GPU platform.

Enumerator:

GPU_PLATFORM_OCL	Open CL.
GPU_PLATFORM_DX11	DirectX 11.
GPU_PLATFORM_DX12	DirectX 12.
GPU_PLATFORM_VULKAN	Vulkan.
GPU_PLATFORM_L0	Level 0.

enum gtpin::GT_ACCESS_TYPE

Bit flags that represent types of accesses to memory regions, registers, etc. Any combination of these flags is a valid access type.

Enumerator:

GT_ACCESS_NONE	No access.
GT_ACCESS_READ	Read-only access.
GT_ACCESS_WRITE	Write-only access.
GT_ACCESS_READ_WRITE	Read-write access.

enum gtpin::SIMD_WIDTH

SIMD width.

Enumerator:

SIMD_WIDTH_1	SIMD 1.
SIMD_WIDTH_4x2	SIMD 4.
SIMD_WIDTH_8	SIMD 8.
SIMD_WIDTH_16	SIMD 16.
SIMD_WIDTH_32	SIMD 32.